Randomness Generation for Secure Hardware Masking – Unrolled Trivium to the Rescue
Authors
Gaëtan Cassiers, Loïc Masure, Charles Momin, Thorben Moos, Amir Moradi, François-Xavier Standaert
Gaëtan Cassiers
Crypto Group, ICTEAM Institute, UCLouvain, Louvain-la-Neuve, Belgium
gaetan dot cassiers at uclouvain dot be
gaetan dot cassiers at uclouvain dot be
Loïc Masure
Université de Montpellier, LIRMM, CNRS, Montpellier, France
loic dot masure at lirmm dot fr
loic dot masure at lirmm dot fr
Thorben Moos
Crypto Group, ICTEAM Institute, UCLouvain, Louvain-la-Neuve, Belgium
thorben dot moos at uclouvain dot be
thorben dot moos at uclouvain dot be
Amir Moradi
TU Darmstadt, Darmstadt, Germany
amir dot moradi at tu-darmstadt dot de
amir dot moradi at tu-darmstadt dot de
François-Xavier Standaert
Crypto Group, ICTEAM Institute, UCLouvain, Louvain-la-Neuve, Belgium
francois-xavier dot standaert at uclouvain dot be
francois-xavier dot standaert at uclouvain dot be
Abstract
Masking is a prominent strategy to protect cryptographic implementations against side-channel analysis. Its popularity arises from the exponential security gains that can be achieved for (approximately) quadratic resource utilization. Many variants of the countermeasure tailored for different optimization goals have been proposed. The common denominator among all of them is the implicit demand for robust and high entropy randomness. Simply assuming that uniformly distributed random bits are available, without taking the cost of their generation into account, leads to a poor understanding of the efficiency vs. security tradeoff of masked implementations. This is especially relevant in case of hardware masking schemes which are known to consume large amounts of random bits per cycle due to parallelism. Currently, there seems to be no consensus on how to most efficiently derive many pseudo-random bits per clock cycle from an initial seed and with properties suitable for masked hardware implementations. In this work, we evaluate a number of building blocks for this purpose and find that hardware-oriented stream ciphers like Trivium and its reduced-security variant Bivium B outperform most competitors when implemented in an unrolled fashion. Unrolled implementations of these primitives enable the flexible generation of many bits per cycle, which is crucial for satisfying the large randomness demands of state-of-the-art masking schemes. According to our analysis, only Linear Feedback Shift Registers (LFSRs), when also unrolled, are capable of producing long non-repetitive sequences of random-looking bits at a higher rate per cycle for the same or lower cost as Trivium and Bivium B. Yet, these instances do not provide black-box security as they generate only linear outputs. We experimentally demonstrate that using multiple output bits from an LFSR in the same masked implementation can violate probing security and even lead to harmful randomness cancellations. Circumventing these problems, and enabling an independent analysis of randomness generation and masking, requires the use of cryptographically stronger primitives like stream ciphers. As a result of our studies, we provide an evidence-based estimate for the cost of securely generating $n$ fresh random bits per cycle. Depending on the desired level of black-box security and operating frequency, this cost can be as low as $20n$ to $30n$ ASIC gate equivalents (GE) or $3n$ to $4n$ FPGA look-up tables (LUTs), where $n$ is the number of random bits required. Our results demonstrate that the cost per bit is (sometimes significantly) lower than estimated in previous works, incentivizing parallelism whenever exploitable. This provides further motivation to potentially move low randomness usage from a primary to a secondary design goal in hardware masking research.
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[KDB+22]
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[KJJ99]
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[KM22a]
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[KM22b]
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[KMMS22]
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[KSM20]
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[KSM22]
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[LBS22]
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[LLL20]
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[LMMR21]
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[MAM16]
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[MCB+22]
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[MM22]
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[MMSS19]
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[MMW18]
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[Moo19]
Thorben Moos. Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments. IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019(3):202–232, 2019. DOI: 10.13154/tches.v2019.i3.202-232
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[MRB18]
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Stjepan Picek, Bohan Yang, Vladimir Rozic, Jo Vliegen, Jori Winderickx, Thomas De Cnudde, and Nele Mentens. PRNGs for Masking Applications and Their Mapping to Evolvable Hardware. In Kerstin Lemke-Rust and Michael Tunstall, editors, Smart Card Research and Advanced Applications - 15th International Conference, CARDIS 2016, Cannes, France, November 7-9, 2016, Revised Selected Papers, volume 10146 of Lecture Notes in Computer Science, pages 209–227. 2016. Springer. DOI: 10.1007/978-3-319-54669-8_13
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[SBHM20]
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Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, and Jean-Luc Danger. High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers, 69(4):534–548, 2020. DOI: 10.1109/TC.2019.2957355
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Bohan Yang, Vladimir Rozic, Milos Grujic, Nele Mentens, and Ingrid Verbauwhede. ES-TRNG: A High-throughput, Low-area True Random Number Generator based on Edge Sampling. IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018(3):267–292, 2018. DOI: 10.13154/tches.v2018.i3.267-292
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History
Submitted: 2024-01-09
Accepted: 2024-06-04
Published: 2024-07-08
Accepted: 2024-06-04
Published: 2024-07-08
How to cite
Gaëtan Cassiers, Loïc Masure, Charles Momin, Thorben Moos, Amir Moradi, and François-Xavier Standaert, Randomness Generation for Secure Hardware Masking – Unrolled Trivium to the Rescue. IACR Communications in Cryptology, vol. 1, no. 2, Jul 08, 2024, doi: 10.62056/akdkp2fgx.
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